AMD Announces Genoa-X, Siena and Turin Server EPYC Processors

AMD Announces Genoa-X, Siena and Turin Server EPYC Processors

At its 2022 Financial Analyst Day presentation event tonight, AMD shared its plans to further develop its EPYC server processors. These are products that have already been released, as well as brand new products targeting market segments that the company did not previously dominate.

The most important but least detailed is the official announcement of the fifth-generation AMD EPYC, codenamed Turin (EPYC 7005), which is expected to appear before the end of 2024. They will be based on the substantially redesigned Zen 5 architecture and use a hybrid 3- and 4-nanometer process technology. Three types of crystals are promised: regular crystals, with 3D V-Cache, and “clouds” (Zen 5c), optimized for increased placement density. The important thing here is that this allows for continuity between generations, which is sure to keep customers happy.

But in the near future, we look forward to the release of AMD EPYC Genoa, which should be released in the fourth quarter of this year. These 5nm processors will have up to 96 Zen 4 cores, 12 DDR5 lanes, PCIe 5.0 and CXL support. The possibility to expand system memory using CXL has now been clearly expressed. The transition to the new technology process and the 1.5x increase in core count provided up to +75% performance improvement (eg Java SPECjbb test).

Genoa will require a new SP5 socket (LGA6096). It will also be ready to accept two other processor options. First up is the all-new Genoa-X, which is easily guessed by the name this is the same Genoa (again up to 96 cores), equipped with an expanded 3D V-Cache L3 cache (from 1GB or more). Like Milan-X, it will target specific classes of workloads that benefit from the increased cache available. For example, computing tasks and DBMS.

Genoa-X will appear in 2023. So it’s worth waiting for the special series in Bergamo. As previously promised, these processors will receive up to 128 cores (and 256 threads) while maintaining compatibility with the SP5 socket. They will be based on 5nm Zen 4c cores, which are somewhat reminiscent of Intel’s E cores. However, Zen 4c’s command set will be the same as Zen 4. AMD didn’t reveal the details of the c-core device again, but it can be assumed that they redesigned the cache hierarchy. They are for hyperscale users who care about resource density rather than just performance.

In 2023, the “small” EPYC will appear under the codename Siena. They are optimized for energy efficiency and offer up to 64 Zen 4 cores. Siena focuses on edge computing and telecommunications. Details about them are also scarce. We might see a hybrid like Ice Lake-D that includes a built-in “smart” network controller.

All new products will use the Zen 4 architecture (4 and 5 nanometers) and will gain new features in addition to the expected performance gains. These include support for AVX-512 (probably not the most complete set) and new instructions for AI workloads that Intel has been showing for several years. But most importantly, the Zen 4 will get the fourth-generation Infinity Architecture interconnect, which will allow you to connect multiple chiplets more closely and at the silicon level (2.5D and 3D packaging).

This paves the way for efficient packaging of multiple functional blocks and support for chip-wide consistency – AMD has confirmed the ability to integrate Xilinx FPGAs and third-party IP blocks. The new interconnect is also CXL 2.0 compliant, which is important for using memory, and future versions will support CXL 3.0 and UCIE. It was the fourth generation of Infinity that allowed AMD to create its first Instinct MI300 server APU.

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